1. Field of the Invention
The present invention relates to an electronic substrate to effectively mount power semiconductor chips thereon and also relates to a power module in which power semiconductor chips are mounted on such an electronic substrate. The present invention further relates to a motor driver and an electric vehicle including such a power module.
2. Description of the Related Art
Some devices with a semiconductor component (which is sometimes generally called a “semiconductor device”) include a substrate, on which an interconnection pattern is defined, and the semiconductor component mounted as a chip (i.e., a semiconductor chip) on that substrate. Such a substrate on which no semiconductor chips have been mounted yet will be referred to herein as an “electronic substrate”. In a device obtained by mounting power semiconductor chips on such an electronic substrate (which will be referred to herein as a “power module” or a “power semiconductor assembly”), a large amount of current of, for example, 50 amperes or more, normally flows through its interconnection pattern. For that reason, the interconnection pattern of such a power module is thicker than that of a normal electronic substrate and may have a thickness of 300 μm, for example.
A power module (or power semiconductor assembly), which includes an electronic substrate and power semiconductor chips mounted thereon and which is used to supply current to a motor, for example, is disclosed in Japanese Laid-Open Publication No. 2002-184907. Hereinafter, the configuration of the power module disclosed in Japanese Laid-Open Publication No. 2002-184907 will be described with reference to FIG. 1.
The power module 100 shown in FIG. 1 includes a metal base substrate 103 and semiconductor chips 105 mounted on the metal base substrate 103. The metal base substrate 103 includes a metallic base plate 101 and an insulating layer 102 provided thereon as a coating.
Pads 104 are provided on the insulating layer 102 of the metal base substrate 103 and the power semiconductor chips 105 are bonded onto those pads 104. Specifically, the semiconductor chips 105 are directly soldered to the pads 104 (where solder is identified by the reference numeral 106 in FIG. 1). Also, the semiconductor chips 105 are connected to a copper foil pattern 107 on the metal base substrate 103 by way of bonding wires 108.
Such a power module 100 may be used to supply current to a three-phase AC motor, for example. FIG. 2 shows an equivalent circuit of a three-phase AC motor driver.
In this motor driver, terminals a and b are connected to a battery and a smoothing capacitor. In the example shown in FIG. 2, a positive potential is applied to the terminal a and a negative potential is applied to the terminal b. Three current paths, each including a pair of power field effect transistor devices (which will be referred to herein as “FET devices”) that are connected in series together, are defined between the terminals a and b. That is to say, a circuit is made up of these six FET devices and the respective gate electrodes of the FET devices are connected in common to a gate driver. The gate driver controls the operations of the FET devices, thereby supplying three-phase AC current to a motor through terminals c, d and e.
In the motor driver shown in FIG. 2, the circuit section inside of the dashed-line box is implemented as the power module (or power semiconductor assembly). Among the components shown in FIG. 2, at least the power module (or power semiconductor assembly) and the gate driver can be integrated together on the same substrate. Thus, an apparatus including a power module and a gate driver with such a configuration will be referred to herein as a “motor driver”.
If the electronic substrate shown in FIG. 1 is used, such a motor driver may be implemented as shown in FIGS. 3A, 3B and 3C. Specifically, FIG. 3A shows a planar layout for a motor driver implemented with the semiconductor device shown in FIG. 1, FIG. 3B is a cross-sectional view thereof, and FIG. 3C shows the encircled portion of FIG. 3B on a larger scale.
As can be seen from FIG. 3B, this motor driver includes a power module having the same configuration as that shown in FIG. 1 and a gate driver for controlling the operations of the FET devices is further provided on its substrate. The respective circuit components are connected together by way of the copper foil pattern provided on the insulating layer and aluminum wires.
The electrodes a, b, c, d and e shown in FIG. 3A respectively correspond to the terminals a, b, c, d and e shown in FIG. 2. Also, in FIG. 3A, the electrodes a and b function as a positive power supply line and a negative power supply line, respectively.
Next, the electronic substrate disclosed in Japanese Laid-Open Publication No. 9-139580 will be described with reference to FIG. 4.
As shown in FIG. 4, the electronic substrate 109 disclosed in Japanese Laid-Open Publication No. 9-139580 has a two-layer interconnect structure. The electronic substrate 109 includes a metal base 110, a first insulating layer 111 provided on the metal base 110, a lower interconnect 112 provided on the first insulating layer 111, a second insulating layer 111′ arranged so as to cover the lower interconnect 112, and an upper interconnect 112′ provided on the second insulating layer 111′. Both of these interconnects 112 and 1121 are made of a copper foil pattern.
In the motor driver shown in FIGS. 3A, 3B and 3C, the electrodes and interconnects thereof have parasitic inductance L. Accordingly, while the FET devices are switching, an overvoltage, which is proportional to the product of a current variation ratio di/dt and the inductance L, is generated. The magnitude of this overvoltage is proportional to the current variation ratio di/dt. Thus, the higher the switching rate of the FET devices, the greater the overvoltage and the more likely the FET devices get damaged.
To protect the FET devices from such damage, either the inductance L or the current variation ratio di/dt needs to be decreased. However, if the current variation ratio di/dt was decreased, then the switching time and the switching loss both would increase and the high-speed switching performance should deteriorate. For that reason, the parasitic inductance L should be reduced.
Thus, in a conventional power module, the parasitic inductance L is reduced by opposing a pair of conductors such that currents flow through the conductors in mutually opposite directions and such that the magnetic fluxes produced by these currents cancel each other. In this case, the opposite currents preferably have approximately the same magnitude. The parasitic inductance L can be reduced even more effectively as the distance between the two opposed conductors is shortened and as their opposing area is broadened.
In the layout shown in FIG. 3A, the direction of current flowing through the electrode a is also opposite to that of current flowing through the electrode b, and the two electrodes a and b are located sufficiently close to each other. However, it is difficult to further reduce the distance between the electrodes a and b or the parasitic inductance L produced because the distance and the inductance L have already been reduced close to their lowest processible limits. In addition, since the electrodes a and b extend substantially parallel to the surface of the substrate, long bonding wires are needed to connect the respective FET devices to the copper foil pattern. As a result, the inductance produced by the bonding wires themselves increases and the overall parasitic inductance also increases unintentionally.
For that reason, instead of trying to further reduce the parasitic inductance, FET devices, specially designed to withstand such a high overvoltage, should be used. Alternatively, additional components need to be provided on the substrate for the purpose of overvoltage protection. As a result, the cost of the power module increases significantly.
Also, even if the multilayer structure shown in FIG. 4 is used to avoid these problems, the following new problems arise.
Specifically, if a power FET device is operated on the upper interconnect 112′, then the FET device will generate a considerable quantity of heat and its temperature will exceed 100° C. In that case, this heat needs to be dissipated away by way of the base. However, the two insulating layers 111 and 111′ provided between the FET device and the base obstruct the smooth heat flow. Thus, the FET device cannot be cooled down sufficiently and may exhibit deteriorated performance or be damaged. Furthermore, if the amounts of currents flowing through the lower and upper interconnects 112 and 112′ are large, then the interconnects 112 and 112′ also generate non-negligible quantities of heat. The lower interconnect 112, in particular, is sandwiched between the first and second insulating layers 111 and 111′, and the heat generated from the lower interconnect 112 cannot be dissipated away so easily.
As can be seen, if such a multilevel interconnect structure is provided on the base, then the insulating layers will obstruct the heat dissipation to a significant degree. Furthermore, the electronic substrate having a two-layer interconnect structure such as that shown in FIG. 4 requires an overly complicated manufacturing process and an excessively high manufacturing cost.